The present invention relates to the field of high-voltage and high-frequency video amplifiers used in BCD (Bipolar/CMOS/DMOS) technology, and in particular, to a class AB amplifier used in CRT (cathode ray tube) screens, computer monitor screens and HDTV (high definition television) screens.
The diagram of FIG. 1 illustrates the principle of a class AB amplifier. The amplifier comprises an output stage 10, which in this case is a complementary stage. Such a stage 10 includes a transistor MP1 and a transistor MN2 connected in series between a high voltage terminal 1 and a low voltage terminal 2. These transistors are respectively MOS transistors (metal-oxide semiconductor) of the P-type and of the N-type. The sources of the transistors MP1 and MN1 are connected together, and are connected to the output node OUT which delivers an output signal Vout. The drain of the transistor MP1 is connected to the terminal 2, and the drain of the transistor MN1 is connected to the terminal 1. The transistors MP1 and MN2 operate in a voltage follower mode.
Furthermore, the amplifier comprises control means 20. The control means 20 includes output nodes A1 and A2 which are respectively connected to the control gate of the transistor MP1 and to the control gate of the transistor MN2.
In a class AB amplifier, the transistors MP1 and MN2 of the output stage 10 are biased so that they are in a zone of operation close to conduction. This reduces the cross-over distortion of the output signal Vout. Biasing the transistors MP1 and MN2 includes creating a bias voltage Vg between the control gates of these transistors. The result of this is that, in a static mode, a quiescent current IQ flows in the output stage 10. The bias voltage Vg is defined by {overscore (Vg)}={overscore (VGSP)}+{overscore (VGSN)}, where {overscore (VGSP)} and {overscore (VGSN)} are respectively the conduction voltages (gate-source voltages) of the transistors MP1 and MN2 for a conduction current having a value equal to the value of the desired quiescent current IQ. The quiescent current IQ in the output stage 10 (also called output quiescent current of the amplifier) must be accurately controlled.
To control the quiescent current IQ in the output stage 10, the control means 20 comprises a floating voltage source 21 connected between the nodes A1 and A2. This voltage source 21 generates a positive floating voltage Vg between the gate of the transistor MN2 and that of the gate transistor MP1.
In the static mode, a current Iin flows in the floating voltage source 21. This is a quiescent current of the control means 20, and is also called the input quiescent current of the amplifier, as opposed to the output quiescent current IQ. In a dynamic mode, a current Iv is taken from the output node A1, or a current is injected into the output node A2. Such a current makes it possible to control the voltage on the input of the voltage follower that includes the output stage 10, and therefore the output signal Vout as a function of an input signal to be amplified.
To reduce the effect of dispersion in component characteristics, which is inherent in silicon integration, the voltage Vg is generally generated from components identical to the transistors MP1 and MN2 of the output stage 10. One embodiment of the voltage source 21 according to the prior art is illustrated by the circuit diagram of FIG. 2.
The voltage source 21 comprises two transistors MP3 and MN4 between the output nodes A1 and A2 of the control means 20, that is, between the respective control gates of the transistors MP1 and MN2. Each transistor is configured as a diode, and the two transistors MP3 and MN4 are connected in series to each other by their respective sources. The two transistors MP3 and MN4 are respectively MOS transistors of the P-type and of the N-type, and are respectively identical to the transistors MP1 and MN2. The control gates of each of the transistors MP3 and MN4 are connected, respectively, to the control gate of the transistor MP1 and to the control gate of the transistor MN4. Configuring transistors MP3 and MN4 as a diode is understood to mean that their drain is connected to their control gate.
The transistors MP3 and MN4 are respectively identical to the transistors MP1 and MN2. Like them, they therefore have a relatively large size. That is, their channel width is relatively large because the transistors MP1 and MN2 must produce a relatively large output current. This known structure therefore has the drawback of introducing a parasitic capacitance on the control gate of the transistor MN2 of the output stage 10. This is the parasitic capacitance denoted Cp in FIG. 2, which exists between the drain of the transistor MN4 and the substrate (the latter conventionally being connected to ground). This parasitic capacitance Cp penalizes this structure in the high-frequency range. This structure is therefore not very suitable for the type of applications planned.
To overcome this drawback, a structure of the type shown in FIG. 3 has already been proposed. This known structure is described in European Patent Application No. 317,015. According to this prior art, the voltage source 21xe2x80x2 comprising a MOS transistor is connected between the output nodes A1 and A2 of the control means 20xe2x80x2, that is, between the respective control gates of the transistors MP1 and MN2. In the example shown in FIG. 3, the MOS transistor is an N-type transistor referenced MN7. In other words, the resistor RD and the transistor MN7 are connected in series between the node B and the node A1.
In addition, the circuit comprises a branch connected in parallel with the branch including the resistor RD and the transistor MN7, between the node B and the node A1. This branch comprises two transistors MN5 and MP6, each one mounted as a diode, which are connected in series by their respective drains between the node B and the node A1. These transistors are MOS transistors of the N-type and of the P-type, respectively. The source of the transistor MN5 is connected to the node A1, and the source of the transistor MP6 is connected to the node B. The control gates of the transistors MP5 and MN6 are connected together. Furthermore, they are connected to the control gate of the transistor MN7.
The transistors MN5 and MP6 may be a much smaller size than the transistors MP1 and MN2. The voltage drop imposed in the resistor RD makes it possible to define the floating voltage Vg between the output nodes A1 and A2 of the control means.
Nevertheless, this structure requires a stable input quiescent current Iin. To obtain this current Iin, it is advantageous to produce a current source with a single resistor whose value is relatively high and which is connected, for example, between the terminal 1 and the output node A2. The value of this resistor is on the order of 3 to 5 kxcexa9 (kilohms). The transistor MN7 must then have a relatively large size (channel width). This is because, with a 3 kxcexa9 resistor, it is necessary to generate a variation xcex94Iv in the current Iv of 15 mA (milliamps) to obtain a variation of the signal on the output OUT equal to 45 V (volts). The large size of the transistor MN7, which implies the existence of a relatively high parasitic capacitance on its drain, also makes this structure not very suitable in the high-frequency range.
In view of the foregoing background, an object of the present invention is to provide a class AB amplifier circuit overcoming the drawbacks of the prior art.
This and other objects, advantages and features in accordance with the present invention are provided by a class AB amplifier circuit comprising a complementary output stage that includes a P-type MOS transistor and an N-type MOS transistor connected in series between a first high-voltage terminal and a low voltage terminal.
The class AB amplifier circuit also comprises control means for biasing the output stage. The control means may comprise a bipolar transistor, the emitter and the collector of which are respectively connected to the control gates of the MOS transistors of the output stage. The bipolar transistor is biased so as to control a bias voltage between the respective control gates of the MOS transistors of the output stage.
The floating voltage source 21 of the circuit diagram of FIG. 1 is produced using a bipolar transistor. The good transconductance of a bipolar transistor, compared to that of a MOS transistor, avoids the drawback mentioned above in relation to the structure of FIG. 4. The current source 22 may then advantageously be produced using a simple resistor having a relatively low value, such as on the order of 3 to 5 kxcexa9.